1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device having a source/drain layer raised from a substrate, wherein occurrence of a low resistance connection (a short) between a source or drain layer and a gate electrode is prevented.
2. Description of the Related Art
In a miniaturized MOSFET, it has been required that a source/drain region at a surface of a substrate is formed with extremely shallow junctions in order to increase a punch-through voltage. However, only to form shallow junctions provokes deterioration in element characteristics due to increase in a parasitic resistance in the source/drain regions. Therefore, in Publication of Unexamined Japanese Patent Application No. Hei 2-222153, there is disclosed an MOSFET in which a lower resistance in a source/drain region is sought by forming a source/drain layer raised from a substrate.
FIGS. 1A to 1C are sectional views showing a method of fabricating a conventional MOSFET in successive process steps. As shown FIG. 1A, a field oxide film 302 is formed at a surface of a silicon substrate 301 by a selective oxidation method and thereby an element region is defined. An oxide film and a polycrystalline silicon film (both not shown) are successively in the order formed on the silicon substrate 301 in the element region and both films are patterned to form a gate oxide film 303 made of the oxide film and a gate electrode 304 made of the polycrystalline silicon film. An oxide film (not shown) of a thickness of 200 to 900 .ANG. is deposited on the entire surface and then etched back by anisotropic dry etching. Thereby a first sidewall insulating film 305 made of the oxide film is formed on a side surface of the gate electrode 304.
Ions are implanted from above the substrate 301 to form a very shallow ion implanted layer 306 at the surface of the substrate 301. The ion implanted layer 306 is formed by implanting n-type ions or p-type ions in the surface of the substrate 301 with a surface concentration of 5.times.10.sup.17 to 1.times.10.sup.20 cm.sup.-3.
As shown in FIG. 1B, silicon films 307a and 307b of thickness of 1000 to 2000 .ANG. are selectively deposited on the top surfaces of the gate electrode 304 and the ion implanted layer 306 by means of a chemical vapor deposition method (CVD method).
As shown in FIG. 1C, an insulating film (not shown) made of an oxide film having a thickness of 1000 to 2000 .ANG. is deposited on the entire surface of the substrate, the insulating film is then etched back by anisotropic dry etching. Thereby, a second sidewall insulating film 308a is formed on side surfaces of the first sidewall insulating film 305 and the silicon film 307a in a contact relation with a surface of the silicon film 307b. And a second sidewall insulating film 308b is also formed on a side surface of the silicon film 307b in a contact relation with the field oxide film 302.
As shown in FIG. 1D, an impurity is doped in a silicon film 307b on the ion implanted layer 306. Thereby a source/drain layer 310 made of the silicon layer is formed on the substrate 301, and a shallow source/drain region 309 are formed in the region where the ion implanted layer 306 is present. Such a source/drain layer 310 forms raised portions from the substrate 301. The source/grain region 309 is formed with a depth larger than each of the ion implanted layers 306 by a small difference.
A titanium silicide layer 311 is formed on the top surface of the source/drain layer 310 on the substrate 301 and on the top surface of the silicon film 307a on the gate electrode 304. The titanium silicide layer 311 is formed in such a manner that first of all, a titanium layer is deposited on the entire surface of the substrate 301 and titanium in the titanium film is reacted with silicon in the silicon layer under the titanium film in a nitrogen atmosphere. Namely, surface portions of the source/drain layer 310 on the substrate 301 and the silicon film 307a on the gate electrode 304 are reacted with titanium in the titanium layer to form the titanium silicide layer 311.
A titanium layer formed on the second sidewall insulating film 308a, 308b, and the field oxide film 302 is reacted with nitrogen in an environmental gas to form a titanium nitride layer. Therefore, if only the titanium nitride layer is selectively removed by wet etching, the titanium silicide layer 311 can be selectively formed on the top surfaces of the source/drain layers 310 and the top surface of the silicon film 307a.
However, in the case where the conventional fabrication method shown in FIG. 1 is adopted, there arises a problem that a low resistance connection is apt to occur between the gate electrode 304 and the source/drain layer 310, or between the source/drain layers 310, themselves adjacent to each other.